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HV7131GP 2004/10/29 v2.4 1 cmos image sensor with image signal processing HV7131GP v2.4
HV7131GP 2004/10/29 v2.4 2 revision history revision script date comments v1.0 2001/11/08/thu ? 2001/11/14/thu - HV7131GP preliminary is released v1.1 2001/12/21/fri - gamma slope table of knee/de-knee is added, and some misprints are corrected v1.2 2002/03/25/mon - knee/de-k nee function is abandoned, instead 10bit adc is implemented. - register descriptions are revised - frame timing is revised. v1.3 2002/04/25/thu - register information is updated v1.4 2002/05/06/mon - data output timing & interface is added v1.5 2002/05/13/tue - chip layout information is revised, and miscellaneous typo errors are corrected v1.6 2002/05/28/tue - chip layout information is omitted for confidentiality, and power consumption information is added. v1.7 2002/06/14/fri - clcc 40 pin diagram added v1.8 2002/12/26/thu. - pkg drawing added v1.9 2003/01/17/fri. - register description revision v2.0 2003/06/04/wed. - 40 pin diagram revision v2.1 2003/07/10/thu.. - enb setting guide information is added v2.2 2003/12/11/thu.. - c[7:0] pad information is added. v2.3 2004/06/26/sat -i2c data hold time revision - external pull-up/ pull-down resistance is added v2.4 2004/10/29/fri - value of snr, dynam ic range, sensitivity is added at features. copyright by magnachip semiconductor lt d., all right reserved 2001, 2002, 2003, 2004 disclaimer this document is a general product description and is subject to change without notice. magnachip semiconductor ltd., assumes no responsibility or liab ility arising from use of circuit described, and no patent licenses are implied.
HV7131GP 2004/10/29 v2.4 3 contents general description ............................................................................................................................... .. 4 features ............................................................................................................................... ..................... 4 block diagram ............................................................................................................................... ........... 5 pin diagram ............................................................................................................................... ............... 7 pin description ............................................................................................................................... .......... 7 functional description ............................................................................................................................ 9 pixel arch itectu re............................................................................................................. ............ 9 enb setting guide information for normal stand- by mode .......................................................... 9 sensor imaging operat ion....................................................................................................... .... 9 10bit on-chip adc .............................................................................................................. ....... 10 gamma corre ction ............................................................................................................... ..... 10 color inter polation ............................................................................................................ ......... 11 color correction & colo r space conv ersion............................................................................. 12 digital gain cont rol ........................................................................................................... ........ 12 output fo rmatting.............................................................................................................. ........ 12 auto exposur e cont rol .......................................................................................................... .... 12 auto white balance ............................................................................................................. ...... 13 spectral char acterist ics....................................................................................................... ...... 13 register description .............................................................................................................................. 1 3 frame ti ming................................................................................................................... ........................ 45 anti-banding conf igurat ion..................................................................................................... ................. 50 data output timing and interface ........................................................................................................ 51 output data format ............................................................................................................................... 51 bayer data format.............................................................................................................. ..................... 53 i2c chip interface ............................................................................................................................... ... 54 ac/dc characteristics .......................................................................................................................... 55 electro-optical characteristics ............................................................................................................ 59 clcc package specification ................................................................................................. 60
HV7131GP 2004/10/29 v2.4 4 general description HV7131GP is a highly integrated single chip cmos color image sensor implemented by proprietary magnachip 0.35um cmos sensor process realizi ng high sensitivity and wide dynamic range. total pixel array size is 652x492, and 652x488 pixels are acti ve. each active pixel composed of 4 transistors has a micro-lens to enhance sensitivity, and conv erts photon energy to analog pixel voltage. on-chip 10bit analog to digital converter (adc) digitize s analog pixel voltage, and on-chip correlated double sampling (cds) scheme reduces fixed pattern nois e (fpn) dramatically. general image processing functions such as gamma correction, color interpolat ion, color correction, co lor space conversion, auto exposure, and auto white balance are implemented to diversify its applications, and various output formats are supported for the sensor to easily interfac e with different video codec chips. the integration of sensor function and image processing functions ma ke HV7131GP especially very suitable for mobile imaging systems such as imt-2000 phone?s video part that requires very low power and system compactness. features ? 1/4 inch optical format ? total pixel : 652 x 492 / active pixel : 652x488 ? 5.6um x 5.6um active square pixel ? micro-lens for high sensitivity ? rgb mosaic color filter array ? on-chip 10 bit adc ? correlated double sampling for reduction of fixed pattern noise ? black level compensation ? gamma correction by programmable piecewise linear approximation ? 3x3 color interpolation ? color correction by programmable 3x3 matrix operation ? color space conversion from rgb to ycbcr ? sub-sampling modes : 1/4, 1/16 ? various output formats : ycbcr 4:2: 2, ycbcr 4:4:4, rgb 4:4:4, bayer ? 8bit / 16bit data bus mode ? automatic exposure control ? automatic white balance control ? frame rate : 30 f/s at 25mhz, hblank = 208, vblank = 8 ? power consumption: 86mw @ 30f/s and 2.8v , 68mw @ 15f/s and 2.8v, 336uw @ power down ? operation voltage range : 2.6v ~ 3.0v, operat ion temperature : -10 ~ +50 degrees celsius
HV7131GP 2004/10/29 v2.4 5 ? package types : clcc 40 pin, cob(ch ip-on-board), cof(chip-on-flex) * to the matter concerning package, wafer business companies are unrelated contents. ? dynamic range : 52 db ? snr max : 42 db ? sensitivity : 3000 mv / lux x sec (green pixel) block diagram vclk y[7:0] c[7:0] vsync hsync resetb mclk enb sck sda pixel array 652 x 492 gamma color interpolation color correction & color space conversion ycbcr digital gain control output formatting timing control row decoder config registers i2c slave auto exposure control auto white balance 10bit adc column cds pga test logic 1. pga : programmable gain amplifier 2. color correction and color space conversion are merged into one matrix operation for hardware simplification rgb gain
HV7131GP 2004/10/29 v2.4 6 pixel array structure metal shielded black level array [2 line] metal shielded black level array [2 line] b g b g g b g b g ? . g r g r g g r g r ? . b g b g g b g b g ? . g r g r g g r g r ? . note: if black level data output is enabled(sctrc[1] set to high) with bayer mode set(sctra[1:0] == 2?b00), data output in the areas of metal shielded black level array can be monitored during 4 line period of hsync right after vsync goes from high state to low state.
HV7131GP 2004/10/29 v2.4 7 pin diagram 16 17 18 19 20 21 22 23 24 2 5 5 4 3 2 1 35 34 33 32 31 30 29 28 27 26 6 7 8 9 10 11 12 13 14 15 HV7131GP clcc 40 pin top view nc y[7] y[6] y[5] y[4] y[3] y[2] y[1] y[0] dgndc c[7] c[6] c[5] c[4] c[3] c[2] c[1] c[0] dgndi dvddi dvddc dgndc a gnd a vdd enb resetb strobe a gnd a vdd nc dvddi dgndi sck sda vsync hsync vclk mclk dgndi dvddc 40 39 38 37 36 HV7131GP clcc 40 pin top view * to the matter concerning package, wafer business companies are unrelated contents. pin description the input mode of hsync/vsync/y[7:0]/c[7:0] is us ed to test internal image processing function in mass production so that it should be not assum ed about slave mode operati on. the device does not support slave mode operation. when 8bit output mode is used, we recommend that c[7:0] be set up as pull-up or pull-down according to i2c regulation. although there is no pull-up or pull-down, it is no influence on function operation and leakage current does not become a problem after stabilization of chip. in case of application with c[7:0] without pull-up or pull-down, any problems were not generated.
HV7131GP 2004/10/29 v2.4 8 pin type symbol description 1-3 b c[2:0] video chrominance data[2:0] 4 g dgndi digital ground for i/o buffer 5 p dvddi digital power for i/o buffer 6 n nc no connection 7-14 o y[7:0] video luminance data[7:0] 15 g dgndc ground for internal digital block 16 p dvddc power for internal digital block 17 g dgndi digital ground for i/o buffer 18 i mclk master input clock 19 o vclk video output clock 20 o hsync video horizontal line synchronization signal. image data is valid, when hsync is high. 21 o vsync video frame synchronization signal. vsync is active at start of image data frame. 22 b sda i2c standard data i/o port 23 i sck i2c clock input 24 g dgndi digital ground for i/o buffer 25 p dvddi digital power for i/o buffer 26 n nc no connection 27 p avdd power for analog block 28 g agnd ground for analog block 29 o strobe strobe signal output 30 i resetb sensor reset, low active 31 i enb sensor sleep mode is contro lled externally by this pin when sleep mode register bit sctrb[4] is low. enb low : sleep mode, enb high : normal mode 32 p avdd power for analog block 33 g agnd ground for analog block 34 g dgndc ground for internal digital block 35 p dvddc power for internal digital block 36-40 b c[7:3] video chrominance data[7:3] * to the matter concerning package, wafer bus iness companies are unrelated contents. note) b: bi-direction pin, p: power pin, g: ground pin, o: output pin, i: input pin
HV7131GP 2004/10/29 v2.4 9 functional description pixel architecture pixel architecture is a 4 transistor nmos pixe l design. the additional use of a dedicated transfer transistor in the architecture reduces most of reset le vel noise so that fixed pattern noise is not visible. furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved. enb setting guide information for normal stand-by mode it is necessary that this kind of initialization sequence for the normal stand-by mode of HV7131GP after system power on dvdd/avdd resetb mclk vsync i2c enb don?t care low low low low system power on initialization sequence 2.086 [mcycle] for logic stable time 2.0 [mcycle] for 1'st vsync out more than 4cycle don?t care 1ms sensor operation sequence sensor power down sequence camera mode video stream 1?st vsync out 1[ms] or more dvdd/avdd resetb mclk vsync i2c enb don?t care low low low low system power on initialization sequence 2.086 [mcycle] for logic stable time 2.0 [mcycle] for 1'st vsync out more than 4cycle don?t care 1ms sensor operation sequence sensor power down sequence camera mode video stream 1?st vsync out 1[ms] or more ex) if mclk = 25[mhz] => 2.086[mcycle] / 25[mhz] = 83.44 ms the time period of enb high value have to keep for 83.44[ms] or more sensor imaging operation imaging operation is implemented by the offset mechanism of integration domain and scan domain(rolling shutter scheme). first integration plane is initiated, and after the programmed integration time is elapsed, scan plane is initia ted, then image data start being produced.
HV7131GP 2004/10/29 v2.4 10 integration time frame 0 time time integration plane frame 0 integration plane frame 1 scan plane frame 0 scan plane frame 1 frame 1 time 10bit on-chip adc on-chip adc converts analog pixel voltage to 10bit digital data. gamma correction piecewise linear gamma approximation method is implemented. ten piece linear segments are supported and user-programmable. gamma slope registers are programmed as the integer value of real slope value that is multiplied by 64.
HV7131GP 2004/10/29 v2.4 11 slope 0 gamma transfer function in out start 0 start 1 slope 1 0 64 128 192 256 512 768 16 32 start 2 start 3 1023 start 9 : : 4 color interpolation three methods are supported to interpolate missing r, g, or b for mosaic image data from pixel array as follows. a) 3x3 linear color interpolation interpolation is done by moving 3x3 interpolati on window by one pixel horizontally and vertically b) 1/4 subsampling color interpolation interpolation is done by moving 2x2 interpolation window by two pixels each time horizontally and vertically. the equation for color interpolati on in each 2x2 window is simple as follows. r1 g1 g2 b1 r = r1 g = (g1 + g2)/2 b = b1 r g b c) 1/16 subsampling color interpolation 1/16 r = (r1 + r2)/2 g = (g1 + g2 + g3 + g4)/4 b = (b1 + b2)/2 r g b r1 g1 g2 b1 r g g b r g g b r2 g3 g4 b2
HV7131GP 2004/10/29 v2.4 12 color correction & color space conversion both of color correction and color space conversion are implemented by 3x3 matr ix operation, so that two stages may be merged into one matrix stage. color correction matrix may be resolved by measuring sensor?s color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. for color space conversion matrix, the equation from ccir-601 st andard is normally used. therefore, the intended single matrix for color correction and color space conversion may be resolved as below. intended single matrix = color space conversion matrix * color correction matrix intended single matrix coefficients are programm able from ?127/64 to 127/64. programming register value for intended single matrix coefficients should be resolved by the following equations. for positive values, cmaxx = integer (real coefficient value x 64); for negative values, cmaxx = two complement (integer (real coefficient value x 64)); real coefficient value values from ?127/64 to 127/64 can be programmed. ccir-601 ycbcr color space conversion equation < conversion equation > y = (77r + 150g + 29b)/256 range: 16 ~ 235 cb = (-44r ?87g + 131b)/256 + 128 range: 16 ~ 240 cr = (131r ? 110g ? 21b)/256 + 128 range: 16 ~ 240 < reverse conversion > r = y + 1.371(cr ? 128) g = y ? 0.698(cr ? 128) ? 0.336(cb ? 128) b = y + 1.732(cb ? 128) in the above equations, r, g, and b are gamma-corrected values. digital gain control y, cb, and cr digital channels are scaled by this blo ck that receives scaling values from auto exposure and auto white balance blocks. scaling reso lution is 1/128 and value range is 1.9 ~ 0.1. output formatting the output formats such as bayer raw data, rgb 4: 4:4, ycbcr 4:4:4, and yc bcr 4:2:2 are supported. possible output bus widths are 8 bits and 16bits, and the sequence of cb and cr are programmable. auto exposure control y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to difference between target y mean value and current frame y mean value.
HV7131GP 2004/10/29 v2.4 13 auto white balance cb/cr frame mean value is calculated every fr ame and according to cb/cr frame mean values? displacement from cb/cr white target point, r/b scaling values for r/b data are resolved. spectral characteristics register description register symbol address (hex) default (hex) description device id devid 00 40 product id, revision no. sensor control a sctra 01 0b oper ation mode, x/y flip, image size sensor control b sctrb 02 00 power down, clock division sensor control c sctrc 03 01 sens or internal control register row start address high rsah 08 00 row start address[8] row start address low rsal 09 02 row start address[7:0] column start address high csah 0a 00 column start address[9:8] column start address low csal 0b 02 column start address[7:0] window height high wihh 0c 01 window height address[8] window height low wihl 0d e0 window height address[7:0] spectral response 0 0.2 0.4 0.6 0.8 1 1.2 1.4 400 450 500 550 600 650 700 wavelength(nm) relative sensitivity b g r
HV7131GP 2004/10/29 v2.4 14 window width high wiwh 0e 02 window width address[9:8] window width low wiwl 0f 80 window width address[7:0] hblank time high hblankh 10 00 hblank time [15:8] hblank time low hblankl 11 d0 hblank time [7:0] vblank time high vblankh 12 00 vblank time [15:8] vblank time low vblankl 13 08 vblank time [7:0] red color gain rcg 14 10 gain for red pixel output green color gain gcg 15 10 gain for green pixel output blue color gain bcg 16 10 gain for blue pixel output preamp gain preamp 17 10 preamp gain for pixel output preamp gain min premin 18 00 preamp gain min value for ae preamp gain max premax 19 3f preamp gain max value for ae preamp gain nominal prenom 1a 10 preamp gain normal value for ae asp bias aspbias 1b 13 amp bias, pixel bias reset clamp rstclmp 1c 07 reset level clamping value adc bias adcbias 20 0f adc bias red pixel black offset oredi 21 7f adc offset value for light-shielded red pixel green pixel black offset ogrni 22 7f adc offset value for light-shielded green pixel blue pixel black offset oblui 23 7f adc offset value for light-shielded blue pixel red pixel active offset oredu 24 ro adc offset value for active red pixel green pixel active offset ogrnu 25 ro adc offset value for active green pixel blue pixel active offset obluu 26 ro adc offset value for active blue pixel black level threshold blcth 27 ff black level threshold value isp function enable ispfen 30 0f image processing functions enable isp output format outfmt 31 39 image data output format control isp output polarity outinv 32 00 output signal polarity control green edge threshold edgeth 33 00 green pixel edge threshold for 3x3 color interpolation color matrix coefficient 11 cma11 34 2e color matrix coefficient 11 color matrix coefficient 12 cma12 35 c5 color matrix coefficient 12 color matrix coefficient 13 cma13 36 0c color matrix coefficient 13 color matrix coefficient 21 cma21 37 0d color matrix coefficient 21
HV7131GP 2004/10/29 v2.4 15 color matrix coefficient 22 cma22 38 3c color matrix coefficient 22 color matrix coefficient 23 cma23 39 f7 color matrix coefficient 23 color matrix coefficient 31 cma31 3a f8 color matrix coefficient 31 color matrix coefficient 32 cma32 3b cf color matrix coefficient 32 color matrix coefficient 33 cma33 3c 39 color matrix coefficient 33 gamma segment point 0 gmap0 40 00 start point for gamma line segment 0 gamma segment point 1 gmap1 41 04 start point for gamma line segment 1 gamma segment point 2 gmap2 42 1c start point for gamma line segment 2 gamma segment point 3 gmap3 43 34 start point for gamma line segment 3 gamma segment point 4 gmap4 44 54 start point for gamma line segment 4 gamma segment point 5 gmap5 45 78 start point for gamma line segment 5 gamma segment point 6 gmap6 46 90 start point for gamma line segment 6 gamma segment point 7 gmap7 47 a4 start point for gamma line segment 7 gamma segment point 8 gmap8 48 e0 start point for gamma line segment 8 gamma segment point 9 gmap9 49 f4 start point for gamma line segment 9 gamma segment slope 0 gmas0 50 40 slope value for gamma line segment 0 gamma segment slope 1 gmas1 51 80 slope value for gamma line segment 1 gamma segment slope 2 gmas2 52 60 slope value for gamma line segment 2 gamma segment slope 3 gmas3 53 40 slope value for gamma line segment 3 gamma segment slope 4 gmas4 54 24 slope value for gamma line segment 4 gamma segment slope 5 gmas5 55 18 slope value for gamma line segment 5 gamma segment slope 6 gmas6 56 14 slope value for gamma line segment 6 gamma segment slope 7 gmas7 57 0f slope value for gamma line segment 7 gamma segment slope 8 gmas8 58 05 slope value for gamma line segment 8 gamma segment slope 9 gmas9 59 02 slope value for gamma line segment 9 ae mode 1 aem1 60 39 auto exposure mode selection 1 ae mode 2 aem2 61 ba auto exposure mode selection 2 integration time high inth 63 07 integration time [23:16] integration time middle intm 64 a1 integration time [15:8] integration time low intl 65 20 integration time [7:0] ae target aetgt 66 70 frame luminance target value ae lock & fine tune boundary aelbnd 67 a2 y frame mean value displacement boundary from ae target where ae goes into lock state. fine tuning boundary is also specified.
HV7131GP 2004/10/29 v2.4 16 ae unlock boundary aeunlck 68 2a y frame mean value displacement from ae target where ae update speed transits from 2x integration unit speed to 1x integration unit speed ae integration step high aei nch 6a 1 integration increm ent step unit [17:16] ae integration step middle aeincm 6b e8 int egration increment step unit [15:8] ae integration step low aeincl 6c 48 in tegration increment step unit [7:0] ae integration limit high aelmh 6d 17 integration time limit [23:16] ae integration limit middle aelmm 6e d7 integration time limit [15:8] ae integration limit low aelml 6f 84 integration time limit [7:0]] awb mode 1 awbm1 70 41 awb mode selection 1 awb mode 2 awbm2 71 2 awb mode selection 2 cb target cbtgt 73 80 cb pl ane target frame mean value. normal white point is 80h. cr target crtgt 74 80 cr pl ane target frame mean value. normal white point is 80h. awb lock boundary awblb 75 2 cb/cr frame mean displacement from cb target and cr target where awb goes into lock state awb unlock boundary awbulb 76 06 displacem ent from ideal white pixel where awb release from lock state awb white pixel boundary awbwpb 77 30 displac ement from ideal white pixel where awb recognizes a pixel as a white pixel affected by light source y digital gain ygain 78 40 y digital gain for auto exposure control cb digital gain cbgain 79 40 cb digital gain for auto white balance control cr digital gain crgain 7a 40 cr digital gain for auto white balance control ae status aest 7b ro ae operation status awb status awbst 7c ro awb operation status y frame mean yfmean 7d ro y frame mean value
HV7131GP 2004/10/29 v2.4 17 cb frame mean cbfmean 7e ro cb frame mean value cr frame mean crfmean 7f ro cr frame mean value minimum anti-banding gain bndgmin 80 08 minimum gain value with anti-banding enabled maximum anti-banding gain bndgmax 81 18 maximum gain value with anti-banding enabled integration-scan plane offset high isofsh 82 ro integrati on-scan plane offset[23:16] integration-scan plane offset middle isofsm 83 ro integrati on-scan plane offset[16:8] integration-scan plane offset low isofsl 84 ro integration-scan plane offset[7:0] awb luminance high boundary awbluhi 8a c8 during cbcr fr ame mean value calculation, a wb discards pixel of which luminance is larger than this register value. awb luminance low boundary awblulo 8b 0a during cbcr frame mean value calculation, a wb discards pixel of which luminance is smaller than this register value. awb valid number awbno 8c 02 a wb update when the number of valid color pixel is larger than (this minimum value x 64) dark bad pixel concealment mode dpcmode 90 0 dark bad pixel concealment mode selection dark bad integration time high dpcinth 91 13 integration time value high byte where filtering operation get s active when dark bad pixel filtering mode is enabled. dark bad integration time middle dpcintm 92 12 integration time value middle byte where filtering operation get s active when dark bad pixel filtering mode is enabled. dark bad integration time low dpcintl 93 d0 integration time value low byte where filtering operation get s active when dark bad pixel filtering mode is enabled. dark bad g threshold dpcgth 94 0c nei ghbor-differential threshold value that specify g dark bad pixel dark bad r/b threshold dpccth 95 0c nei ghbor-differential threshold value that specify r/b dark bad pixel
HV7131GP 2004/10/29 v2.4 18 device id [devid : 00h : 40h] 7 6 5 4 3 2 1 0 product id revision number 0 1 0 0 0 0 0 0 high nibble represents sensor array resoluti on, low nibble represents revision number. sensor control a [sctra : 01h : 0bh] 7 6 5 4 3 2 1 0 operation mode x-flip y-flip video mode 0 0 0 0 1 0 1 1 category operation mode note 1111 at cds operation, reset and image bit-lines are all written to high. this mode is just for monitoring purpose. 1110 at cds operation, image bit-line is written to high. in this mode, all bayer data output are 8?h00. 1101 at cds operation, reset bit-line is written to high. in this mode, all bayer data output are 8?hff. testc 1100 reserved 10x1 adc overflow test with cds output disconnected. in this mode, all bayer data output are 8?hff. testa 10x0 adc underflow test with cds output disconnected. in this mode, all bayer data output are 8?h00. testi 011x image processing function test 0101 i2c state machine test testb 0100 sensor operation state machine test normal 0000 normal imaging operation x-flip image is horizontally flipped y-flip image is vertically flipped 11 3x3 color interpolation 10 1/4 subsampling mode 01 1/16 subsampling mode video mode 00 bayer output mode
HV7131GP 2004/10/29 v2.4 19 sensor control b [sctrb : 02h : 00h] 7 6 5 4 3 2 1 0 ae/awb block sleep datapath block sleep analog block sleep sleep mode strobe enable clock division 0 0 0 0 0 0 0 0 < clock acronym definition > mcf : master clock frequency dcf : divided clock frequency scf : sensor clock frequency icf : image processing clock frequency vcf : video clock frequency lcf : line clock frequency < clock frequency relation > mcf : mcf dcf : mcf/clock division scf : dcf/2 icf scf for 3x3 interpolation, scf/2 for 1/4 subsampling mode scf/4 for 1/16 subsampling mode vcf : icf for 16bit output, icf*2 for 8bit output lcf : 1/(hblank period + hsync period) ae/awb block sleep ae/awb block goes into sleep mode with this bit set to high. datapath block sleep image processing datapath block goes into sleep mode with this bit set to high. analog block sleep all internal analog block goes into sleep mode with this bit set to high. with all digital block sleep active, s ensor goes into power down mode. sleep mode all internal digital and analog block goes into sleep with this bit set to high. strobe enable when strobe signal is enabled by this bit, strobe pin will indicates when strobe light should be splashed in the dark environment to get adequate lighted image. clock division divides input master clock(imc) for internal use. internal divided clock frequency(dcf) is defined as master clock frequency(mcf) divided by specified clock divisor. internal di vided clock frequency(dcf) is as follows. 000 : mcf, 001 : mcf/2, 010 : mcf/4, 011 : mcf/8 100 : mcf/16, 101 : mcf/32, 110 : mcf/64, 111 : mcf/128 sensor control c [sctrc : 03h : 01h]
HV7131GP 2004/10/29 v2.4 20 7 6 5 4 3 2 1 0 black level average output y[7:0] pad output with hsync high c[7:0] pad output with 8bit mode hsync in vblank reserved unified gain black level data enable black level compens- ation 0 0 0 0 0 0 0 1 black level average output this bit enable r/g/b active offset registers[24h-26h] to represent black level average value, instead of updated active offset values y[7:0] pad output with hsync high with this bit set to high, y[7:0] pads go into tri-state when hsync is inactive. c[7:0] pad output with 8bit mode with this bit set to high, c[7:0] pads go into zero driving state with 8bit output mode enabled. otherwise, t hese pads go into tri-state. hsync in vblank vblank is equivalent to vsy nc, and hsync is the inversion of hblank, and this bit control whether hsync is active or not when vblank unit is lcf. vsync (vblank) hsync unified gain g gain is used for r, g, and b analog gain black level data enable hsync is generated for light-shielded pixels in 4 lines. black level compensation black level average values of light-shielded pixels are compensated when active image data is produced. row start address high [rsah : 08h : 0h] 7 6 5 4 3 2 1 0 reserved row start address high 0 0 0 0 0 0 0 0 row start address low [rsal : 09h : 02h]
HV7131GP 2004/10/29 v2.4 21 7 6 5 4 3 2 1 0 row start address low 0 0 0 0 0 0 1 0 row start address register defines the ro w start address of image read out operation. column start address high [csah : 0ah : 0h] 7 6 5 4 3 2 1 0 reserved column start address high 0 0 0 0 0 0 0 0 column start address low [csal : 0bh : 02h] 7 6 5 4 3 2 1 0 column start address low 0 0 0 0 0 0 1 0 column start address register defines the co lumn start address of image read out operation. window height high [wihh : 0ch : 1h] 7 6 5 4 3 2 1 0 reserved window height high 0 0 0 0 0 0 0 1 window height low [wihl : 0dh : e0h] 7 6 5 4 3 2 1 0 window height low 1 1 1 0 0 0 0 0 window height register defines the height of image to be read out. window width high [wiwh : 0eh : 2h] 7 6 5 4 3 2 1 0 reserved window width high 0 0 0 0 0 0 1 0 window width low [wiwl : 0fh : 80h]
HV7131GP 2004/10/29 v2.4 22 7 6 5 4 3 2 1 0 window width low 1 0 0 0 0 0 0 0 window width address register defines the width of image to be read out. hblank time high [hblankh : 10h : 00h] 7 6 5 4 3 2 1 0 hblank time high 0 0 0 0 0 0 0 0 hblank time low [hblankl : 11h : d0h] 7 6 5 4 3 2 1 0 hblank time low 1 1 0 1 0 0 0 0 hblank time register defines data blank time between current line and next line by using sensor clock period unit (1/scf), and should be larger than 208(d0h). vblank time high[vblank : 12h : 00h] 7 6 5 4 3 2 1 0 vblank time high 0 0 0 0 0 0 0 0 vblank time low[vblank : 13h : 08h] 7 6 5 4 3 2 1 0 vblank time low 0 0 0 0 1 0 0 0 vblank time register defines active high durat ion of vsync output. active high vsync indicates frame boundary between continuous frames. for vsync-h sync timing relation in the frame transition, please refer to frame timing section. each sensor has a little different photo-diode characteristics so that the sensor provides internal adjustment registers that calibrate internal sensing circuit in order to get optimal performance. sensor characteristics adjustment registers are as below. r color gain [rcg : 14h : 10h]
HV7131GP 2004/10/29 v2.4 23 7 6 5 4 3 2 1 0 reserved r color gain 0 0 0 1 0 0 0 0 g color gain [gcg : 15h : 10h] 7 6 5 4 3 2 1 0 reserved g color gain 0 0 0 1 0 0 0 0 b color gain [bcg : 16h : 10h] 7 6 5 4 3 2 1 0 reserved b color gain 0 0 0 1 0 0 0 0 there are three color gain registers for r, g, b pixe ls, respectively. programmable range is from 0.5x ~ 2.5x. effective gain = 0.5 + b<5: 0>/32. these registers may be used for white balance and color effect with independent r,g,b color control. default gain is 1x. preamp gain [preamp : 17h : 10h] 7 6 5 4 3 2 1 0 preamp gain 0 0 0 1 0 0 0 0 preamp gain is common gain for r, g, b channel and used for auto exposure control. programmable range is from 0.5x ~ 16.5x. default gain is 1.5x. gain = 0.5 + b<7:0>/16 preamp gain min [premin : 18h : 00h] 7 6 5 4 3 2 1 0 preamp gain min 0 0 0 0 0 0 0 0 preamp gain min is minimum value of preamp gain when sensor adjusts pre-amplifier gain for auto exposure control. programmable range is same as preamp gain. recommended value is 0.5x. preamp gain max [premax : 19h : 3fh] 7 6 5 4 3 2 1 0 preamp gain max 0 0 1 1 1 1 1 1 preamp gain max is maximum value of preamp gain when sensor adjusts preamp gain for auto
HV7131GP 2004/10/29 v2.4 24 exposure control. programmable range is same as preamp gain. recommended value is 16.5x. preamp gain normal [prenor : 1ah : 10h] 7 6 5 4 3 2 1 0 preamp gain normal 0 0 0 1 0 0 0 0 preamp gain normal is reference value of pr eamp gain when sensor adjusts preamp gain for auto exposure control. first, sensor c ontrols integration time before adj usting preamp gain for auto exposure control. after integration time is changed to the minimum or maximum value, sensor adjusts preamp gain from this register value. refe r to figure of ae mode1 register(60h). programmable range is same as preamp gain. recommended value is 1.5x. asp bias [aspbias : 1bh : 13h] 7 6 5 4 3 2 1 0 reserved pixel bias amp bias 0 0 0 1 0 0 1 1 pixel bias controls the amount of current in inter nal pixel bias circuit to amplify pixel output effectively. the larger regi ster value increases the amount of current. amplifier bias controls the amount of current in inter nal amplifier bias circuit to amplify pixel output effectively. the larger r egister value increases the amount of current. reset level clamp [rstclmp : 1ch : 07h] 7 6 5 4 3 2 1 0 reserved reset level clamp 0 0 0 0 0 1 1 1 because extremely bright image like sun affects rese t data voltage of pixel to lower, bright image is captured as black image in image sensor regardle ss of correlated double sampling. to solve this extraordinary phenomenon, we adopt the method to cl amp reset data voltage. reset level clamp controls the reset data voltage to prevent inversion of extremely bright image. the larger register value clamps the reset data level at highest voltage level. de fault value is 7 to clamp the reset data level at appropriate voltage level. adc bias [adcbias : 20h : 0fh]
HV7131GP 2004/10/29 v2.4 25 7 6 5 4 3 2 1 0 reserved adc bias 0 0 0 0 1 1 1 1 adc bias controls the amount of cu rrent in adc bias circuit to oper ate adc effectively. the larger register value increases the amount of current. red pixel black offset [oredi : 21h : 7fh] 7 6 5 4 3 2 1 0 red pixel black offset 0 1 1 1 1 1 1 1 green pixel black offset [ogrni : 22h : 7fh] 7 6 5 4 3 2 1 0 green pixel black offset 0 1 1 1 1 1 1 1 blue pixel black offset [oblui : 23h : 7fh] 7 6 5 4 3 2 1 0 blue pixel black offset 0 1 1 1 1 1 1 1 these registers control the offset voltage of adc that changes the bl ack level value for light-shielded pixels, red, green and blue pixel respectively. r egister bit functions are composed as follows. pixel black offset[7] the bit specifies whether to subtract or add offset voltage in adc input for light-shielded pixels. pixel black offset[6:0] this value specifies the amount of offset voltage for light-shielded pixels. red pixel active offset [oredu : 24h : ro] 7 6 5 4 3 2 1 0 red pixel active offset ro ro ro ro ro ro ro ro green pixel active offset [ogrnu : 25h : ro] 7 6 5 4 3 2 1 0
HV7131GP 2004/10/29 v2.4 26 green pixel active offset ro ro ro ro ro ro ro ro blue pixel active offset [obluu : 26h : ro] 7 6 5 4 3 2 1 0 blue pixel active offset ro ro ro ro ro ro ro ro these registers control the offset voltage of adc that changes the black level value for active pixels, red, green and blue pixel respectively. the registers are internally updated by black level compensation logic, and are read-only registers. register bit functions are composed as follows. pixel active offset[7] the bit specifies whether to subtract or add offset voltage in adc input for active pixels. pixel active offset[6:0] this value specifies t he amount of offset voltage for active pixels. black level threshold [blcth : 27h : ffh] 7 6 5 4 3 2 1 0 black level threshold 1 1 1 1 1 1 1 1 the register specifies the maximum value which det ermines whether light-shielded pixel output is valid. when light-shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation. isp function enable [ispfen : 30h : 0fh] 7 6 5 4 3 2 1 0 reserved matrix operation color interpolation gamma correction reserved 0 0 0 0 1 1 1 1 matrix conversion in HV7131GP, two matrix operations of color correction & color space conversion are merged into one matrix oper ation. with this bit set to high, the matrix operation is enabled, and ot herwise r/g/b data is output through output formatter. color interpolation with sctra[1:0] set to 3x3 color inte rpolation, this bit control the final channel between color interpolated r/g/b and bayer data. with this bit set
HV7131GP 2004/10/29 v2.4 27 to low, r/g/b channels for one pixel are fed with the same one bayer value so that image similar to black & white is produced. gamma correction with this bit set to high, 10 segments piecewise approximate gamma is enabled. output format [outfmt : 31h : 39h] 7 6 5 4 3 2 1 0 gamma- corrected bayer bayer 8bit output cb first y first 8 bit output reserved ycbcr 4:4:4 ycbcr 4:2:2 0 0 1 1 1 0 0 1 gamma-corrected bayer bayer data that are gamma corrected is output when bayer mode is set in sctra register. bayer 8bit output bayer data is output with 8bit mode. two lsb of 10 bit bayer data is stripped out. cb first cb pixel in front of cr pi xel in 16bit or 8bit video data output modes y first y pixel in front of cb and cr pixe ls in 8bit video output mode. this option is meaningful only with 8bit output mode. 8 bit output image data is produced only in y[7:0]. c[7:0] should be discarded ycbcr 4:4:4 ycbcr 24bit data for a pixel is produced with 16bit output mode. with color space conversion disabled, rgb 24bit dat a for a pixel is produced in this mode. this mode is meaningful only with 16bit output mode. ycbcr 4:2:2 ycbcr data for a pixel is produced with 8/16 output mode output inversion[outinv : 32h : 0h] 7 6 5 4 3 2 1 0 reserved clocked hsync vsync inversion hsync inversion vclk inversion 0 0 0 0 0 0 0 0 clocked hsync in hsync, vclk is embedded, t hat is, hsync is toggling at vclk rate during normal hsync time vsync inversion vsync output polarity is inverted hsync inversion hsync output polarity is inverted
HV7131GP 2004/10/29 v2.4 28 vclk inversion vclk output polarity is inverted green edge threshold[edgeth : 33h : 00h] 7 6 5 4 3 2 1 0 green edge threshold 0 0 0 0 0 0 0 0 in 3x3 color interpolation mode, missing g pixe l is interpolated with edge detection considering neighbor g pixels, and this register controls edge thre shold to select edge direction. the smaller value means that the more patterns are recognized as edge, and image may get sharper, but not always. color matrix coefficients both of color correction and color space conversion are implemented by 3x3 matr ix operation, so that two stages may be merged into one matrix stage. color correction matrix may be resolved by measuring sensor?s color spread characteristics for primary color source and calculating the inverse matrix of color spread matrix. for color space conversion matrix, the equation from ccir-601 st andard is normally used. therefore, the intended single matrix for color correction and color space conversion may be resolved as below. intended single matrix = color space conversion matrix * color correction matrix intended single matrix coefficients are programm able from ?127/64 to 127/64. programming register value for intended single matrix coefficients should be resolved by the following equations. for positive values, cmaxx = integer(realcoefficientvalue x 64); for negative values, cmaxx = twocomplem ent(integer(realcoefficientvalue x 64)); realcoefficientvalue values from ?127/64 to 127/64 can be programmed. ccir-601 ycbcr color space conversion equation < conversion equation > y = (77r + 150g + 29b)/256 range: 16 ~ 235 cb = (-44r ?87g + 131b)/256 + 128 range: 16 ~ 240 cr = (131r ? 110g ? 21b)/256 + 128 range: 16 ~ 240 < reverse conversion > r = y + 1.371(cr ? 128) g = y ? 0.698(cr ? 128) ? 0.336(cb ? 128) b = y + 1.732(cb ? 128) in the above equations, r, g, and b are gamma-corrected values color matrix coefficient 11 [cma11 : 34h : 2eh] 7 6 5 4 3 2 1 0
HV7131GP 2004/10/29 v2.4 29 color matrix coefficient 11 0 0 1 0 1 1 1 0 color matrix coefficient 12 [cma12 : 35h : c5h] 7 6 5 4 3 2 1 0 color matrix coefficient 12 1 1 0 0 0 1 0 1 color matrix coefficient 13 [cma13 : 36h : 0ch] 7 6 5 4 3 2 1 0 color matrix coefficient 13 0 0 0 0 1 1 0 0 color matrix coefficient 21 [cma21 : 37h : 0dh] 7 6 5 4 3 2 1 0 color matrix coefficient 21 0 0 0 0 1 1 0 1 color matrix coefficient 22 [cma22 : 38h : 3ch] 7 6 5 4 3 2 1 0 color matrix coefficient 22 0 0 1 1 1 1 0 0 color matrix coefficient 23 [cma23 : 39h : f7h] 7 6 5 4 3 2 1 0 color matrix coefficient 23 1 1 1 1 0 1 1 1 color matrix coefficient 31 [cma31 : 3ah : f8h] 7 6 5 4 3 2 1 0 color matrix coefficient 31 1 1 1 1 1 0 0 0 color matrix coefficient 32 [cma32 : 3bh : cfh] 7 6 5 4 3 2 1 0
HV7131GP 2004/10/29 v2.4 30 color matrix coefficient 32 1 1 0 0 1 1 1 1 color matrix coefficient 33 [cma33 : 3ch : 39h] 7 6 5 4 3 2 1 0 color matrix coefficient 33 0 0 1 1 1 0 0 1 gamma segment start points gamma segment start points specify the start points of nine line segments for piecewise gamma approximation. current default gamma curve is very selected for optimum gray gradation. gamma point 0 [gamp0 : 40h : 00h] 7 6 5 4 3 2 1 0 gamma point 0 0 0 0 0 0 0 0 0 gamma point 1 [gmap1 : 41h : 04h] 7 6 5 4 3 2 1 0 gamma point 1 0 0 0 0 0 1 0 0 gamma point 2 [gmap2 : 42h : 1ch] 7 6 5 4 3 2 1 0 gamma point 2 0 0 0 1 1 1 0 0 gamma point 3 [gmap3 : 43h : 34h] 7 6 5 4 3 2 1 0 gamma point 3 0 0 1 1 0 1 0 0 gamma point 4 [gmap4 : 44h : 54h] 7 6 5 4 3 2 1 0 gamma point 4
HV7131GP 2004/10/29 v2.4 31 0 1 0 1 0 1 0 0 gamma point 5 [gmap5 : 45h : 78h] 7 6 5 4 3 2 1 0 gamma point 5 0 1 1 1 1 0 0 0 gamma point 6 [gmap6 : 46h : 90h] 7 6 5 4 3 2 1 0 gamma point 6 1 0 0 1 0 0 0 0 gamma point 7 [gmap7 : 47h : a4h] 7 6 5 4 3 2 1 0 gamma point 7 1 0- 1 0 0 1 0 0 gamma point 8 [gmap8 : 48h : e0h] 7 6 5 4 3 2 1 0 gamma point 8 1 1 1 0 0 0 0 0 gamma point 9 [gmap9 : 49h : f4h] 7 6 5 4 3 2 1 0 gamma point 9 1 1 1 1 0 1 0 0 gamma slope values gamma slope registers are programmed as the integer value of real slope value that is multiplied by 64. gamma slope 0 [gmas0 : 50h : 40h] 7 6 5 4 3 2 1 0 gamma slope 0 0 1 0 0 0 0 0 0
HV7131GP 2004/10/29 v2.4 32 gamma slope 1 [gmas1 : 51h : 80h] 7 6 5 4 3 2 1 0 gamma slope 1 1 0 0 0 0 0 0 0 gamma slope 2 [gmas2 : 52h : 60h] 7 6 5 4 3 2 1 0 gamma slope 1 0 1 1 0 0 0 0 0 gamma slope 3 [gmas3 : 53h : 40h] 7 6 5 4 3 2 1 0 gamma slope 3 0 1 0 0 0 0 0 0 gamma slope 4 [gmas4 : 54h : 24h] 7 6 5 4 3 2 1 0 gamma slope 4 0 0 1 0 0 1 0 0 gamma slope 5 [gmas5 : 55h : 18h] 7 6 5 4 3 2 1 0 gamma slope 5 0 0 0 1 1 0 0 0 gamma slope 6 [gmas6 : 56h : 14h] 7 6 5 4 3 2 1 0 gamma slope 6 0 0 0 1 0 1 0 0 gamma slope 7 [gmas7 : 57h : 0fh] 7 6 5 4 3 2 1 0 gamma slope 7 0 0 0 0 1 1 1 1
HV7131GP 2004/10/29 v2.4 33 gamma slope 8 [gmas8 : 58h : 05h] 7 6 5 4 3 2 1 0 gamma slope 8 0 0 0 0 0 1 0 1 gamma slope 9 [gmas9 : 59h : 02h] 7 6 5 4 3 2 1 0 gamma slope 9 0 0 0 0 0 0 1 0 auto exposure y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to the displacement betw een current frame y mean value and target y mean value. ae unlock boundary [68h] ae target [66h] ae lock boundary [67h] ae lock boundary [67h] ae unlock boundary [68h] 70h y frame mean ffh 0h ae mode control 1 [aem1 : 60h : 39h] 7 6 5 4 3 2 1 0 anti ? banding enable full window window mode ae speed ae mode
HV7131GP 2004/10/29 v2.4 34 0 0 1 1 1 0 0 1 anti-banding enable when anti-banding is enabled, ae initializes integration time registers[63h-65h] to 4 x anti-banding step value[6ah-6ch], and integration increment/decrement amount is set to anti-banding step value in order to remove banding noise caused by intrinsic energy waveform of light sources. banding noise is inherent in cmos image sensor that adopts rolling shutter scheme for image acquisition. in this mode, ae operates with very large unit, typically a reciprocal of (2 x power line frequency), so that minute integration time tuning is not liable. therefore, this mode is recommended for only indoor use. full window with this bit set to high, window mode is discarded and full image data is accounted for ae y frame mean evaluation 11 1/8 center weighted window mode. weighting ratio is 8:1 for inside area vs. outside area 10 1/8 center only window mode. 01 1/4 center weighted window mode. weighting ratio is 4:1 for inside area vs. outside area window mode 00 1/4 center only window mode. ae speed (fast)11 - 10 - 01 - 00(slow) 11 gain-only control mode. only preamp gain is controlled to get optimum exposure state. 10 time-only control mode. only int egration time is controlled to get optimum exposure state. 01 time-gain control mode. integration time and preamp gain are controlled to get optimum exposure state. ae mode 00 ae function is disabled ae mode control 2 [aem2 : 61h : bah] 7 6 5 4 3 2 1 0 gain speed integration time fine tune preamp gain fine tune anti- banding minimum break ae subsampli- ng mode ae analog gain control ae digital gain control 1 0 1 1 1 0 1 0
HV7131GP 2004/10/29 v2.4 35 gain speed gain update speed is specified as follows. (fast)11 - 10 - 01 - 00(slow) integration time fine tune integration time fine tuning is performed when ae arrive around ae fine tune boundary to settle into ae lock state smoothly. preamp gain fine tune preamp gain fine tuning is performed when ae arrive around ae fine tune boundary to settle into ae lock state smoothly. anti-banding minimum break when ae is still of out lock state despite that ae preamp analog gain update value exceeds preamp minimum gain value(18h) and integration time(63h-65h) is reached to ae anti -banding step(6ah-6ch), integration time(63h-65h) is broken to less than ae anti-banding step(6ah-6ch). ae subsampling mode ae statistics is executed on 1/4 of original image data to save power consumption ae analog gain control ae updates preamp gain register(17h) in order to reach optimum exposure state ae digital gain control ae updates y digital gain register(78h) in order to reach optimum exposure state integration time high [inth: 63h : 07h] 7 6 5 4 3 2 1 0 integration time high [23:16] 0 0 0 0 0 1 1 1 integration time middle [intm: 64h: a1h] 7 6 5 4 3 2 1 0 integration time middle[15:8] 1 0 1 0 0 0 0 1 integration time low [intl: 65h: 20h] 7 6 5 4 3 2 1 0 integration time low[7:0] 0 0 1 0 0 0 0 0 integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal adc processi ng. integration time is equivalent to exposure time of general camera so that int egration time need to be increased in dark environment
HV7131GP 2004/10/29 v2.4 36 and decreased according to lighting condition. maxi mum integration time is register maximum value(2 24 -1) x sensor clock period(80ns, sc f 12.5mhz @ dcf 25mhz) = 1.34sec. ae target [aetgt : 66h : 70h] 7 6 5 4 3 2 1 0 ae target 0 1 1 1 0 0 0 0 this register defines the target luminance value for ae operation. ae lock boundary [aelbnd : 67h : a2h] 7 6 5 4 3 2 1 0 ae fine boundary ae lock boundary 1 0 1 0 0 0 1 0 ae lock boundary specifies the displacement of y frame mean value(7dh) from ae target in which ae goes into lock state. with anti-banding is enabl ed, this displacement condition is discarded, and instead ae unlock boundary is used as lock boundary. ae fine boundary specifies the displacement of y fr ame mean value(7dh) from ae target in which ae start to tune fine integration time or preamp gai n in order to goes into lock state smoothly. ae unlock boundary [aeunlck : 68h : 2ah] 7 6 5 4 3 2 1 0 ae unlock boundary 0 0 1 0 1 0 1 0 ae unlock boundary 0 specifies y frame mean displace ment from ae target where integration time increment/decrement speed changes from 2x (integrati on unit step) to 1x (integration unit step). in anti- banding mode, this boundary is used as lock boundary for exposure control. ae anti-banding step high [aeanth : 6ah : 1h] 7 6 5 4 3 2 1 0 reserved ae anti-banding step high 0 0 0 0 0 0 0 1 ae anti-banding step middle [aeantm : 6bh : e8h] 7 6 5 4 3 2 1 0
HV7131GP 2004/10/29 v2.4 37 ae anti-banding step high 1 1 1 0 1 0 0 0 ae anti-banding step low [aeantl : 6ch : 48h] 7 6 5 4 3 2 1 0 ae anti-banding step low 0 1 0 0 1 0 0 0 ae anti-banding step specifies integration time uni t value that ae uses when anti-banding is enabled. anti-banding step value is resolved by the following equation. anti-banding step value = sensor operati on frequency (scf) / (2x power line frequency) the default value is set with scf 12.5mhz, 50hz power line, that is, anti-banding step value = 12.5mhz / (2 x 50) = 125000d = 1e848h ae integration time limit high [aelmh : 6dh : 17h] 7 6 5 4 3 2 1 0 ae integration time limit high 0 0 0 1 0 1 1 1 ae integration time limit middle [aelmm : 6eh : d7h] 7 6 5 4 3 2 1 0 ae integration time limit middle 1 1 0 1 0 1 1 1 ae integration time limit low [aelml : 6fh : 84h] 7 6 5 4 3 2 1 0 ae integration time limit low 1 0 0 0 0 1 0 0 these three registers define the maximum integration ti me value that is allowed to sensor operation. it is desirable to set the value to multiples of ae anti-banding step to easily operate with anti-banding mode enabled. the default value is set to 1/8sec with scf set to 25mhz 12.5mhz / 8 = 1,562,500 = 17d784
HV7131GP 2004/10/29 v2.4 38 auto white balance cb/cr frame mean value is calculated every fr ame and according to cb/cr frame mean values? displacement from cb/cr white target point, r/b scaling values for r/b data are resolved. aw b unlock boundary [76h] cb/cr target [73h-74h] aw b lock boundary [75h] aw b w hite pixel boundary [77 h aw b lock boundary [75h] aw b unlock boundary [76h] aw b w hite pixel boundary [77 h 80h cb/cr fram e mean ffh 0h awb mode control 1 [awbm : 70h : 41h] 7 6 5 4 3 2 1 0 reserved full window window mode awb speed reserved awb on 0 1 0 0 0 0 0 1 full window with this bit set to high, window mode is discarded and full image data is accounted for ae y frame mean evaluation 11 1/8 center weighted window mode. weighting ratio is 8:1 for inside area vs. outside area 10 1/8 center only window mode. 01 1/4 center weighted window mode. weighting ratio is 4:1 for inside area vs. outside area window mode 00 1/4 center only window mode.
HV7131GP 2004/10/29 v2.4 39 awb speed (fast)11 - 10 - 01 - 00(slow) awb on auto white balance control enabled awb mode control 2 [aem2 : 71h : 02h] 7 6 5 4 3 2 1 0 reserved awb low speed awb subsampli- ng mode awb analog gain control awb digital gain control 0 0 0 0 0 0 1 0 awb low speed with this bit set to high, analog gain speed is decreased to 1/4 of the normal speed. awb subsampling mode awb statistics is executed on 1/4 of original image data to save power consumption awb analog gain control awb updates r/b gain registers(14h,16h) in order to reach optimum white balance state awb digital gain control awb updates cb/cr digital gain regi sters(79h,7ah) in order to reach optimum white balance state cb target [cbtgt : 73h : 80h] 7 6 5 4 3 2 1 0 cb target 1 0 0 0 0 0 0 0 this register defines cb target frame mean value for awb operation. cr target [crtgt : 74h : 80h] 7 6 5 4 3 2 1 0 cr target 1 0 0 0 0 0 0 0 this register defines cr target frame mean value for awb operation. awb lock boundary [awblb : 75h : 2h] 7 6 5 4 3 2 1 0 reserved awb lock boundary
HV7131GP 2004/10/29 v2.4 40 0 0 0 0 0 0 1 0 it specifies cb/cr frame mean values? displacement from cb/cr target (73h-74h) value where awb goes into lock state. awb unlock boundary [awbub : 76h : 06h] 7 6 5 4 3 2 1 0 awb unlock boundary 0 0 0 0 0 1 1 0 it specifies cb/cr frame mean values? displacem ent from cb/cr target (73h-74h) where awb is released from lock state. awb operation retain s lock state unless cb/cr frame mean values? displacement value exceeds this boundary. t he value should be larger awb lock boundary. awb white pixel boundary [awbwpb : 77h : 30h] 7 6 5 4 3 2 1 0 awb white pixel boundary 0 0 1 1 0 0 0 0 when cb/cr frame mean values? displacement from cb/cr target exceeds awb white pixel boundary value, awb accept frame color as it is and does not try to correct white balance deviation. y digital gain [ygain : 78h : 40h] 7 6 5 4 3 2 1 0 y digital gain 0 1 0 0 0 0 0 0 the register represents the current y digital gain val ue (1/64 resolution) in digital gain block, and is updated every frame by ae logic when ae digital gain update mode is active. cb digital gain [cbgain : 79h : 40] 7 6 5 4 3 2 1 0 cb digital gain 0 1 0 0 0 0 0 0 the register represents the current cb digital gain va lue (1/64 resolution) in digital gain block, and is updated every frame by awb logic when awb digital gain update mode is active. cr digital gain [awbsclb : 7ah : 40h] 7 6 5 4 3 2 1 0 cr digital gain
HV7131GP 2004/10/29 v2.4 41 0 1 0 0 0 0 0 0 the register represents the current cr scaling val ue(1/64 resolution) in digital gain block, and is updated every frame by awb logic when awb digital gain update mode is active. ae status [aest : 7bh : ro] 7 6 5 4 3 2 1 0 ae mode state ae lock state ro ro ro ro ro ro ro ro ae mode state this nibble represents the mode where in ternal y plane fsm is currently placed among time-gain control, time-only c ontrol, or gain-only control modes. ae lock state y channel fsm status, ?0000? means that ae y plane is in lock state awb status [awbst : 7ch : ro] 7 6 5 4 3 2 1 0 reserved ae/awb lock cb lock state cr lock state ro ro ro ro ro ro ro ro ae/awb lock this single status bit indicates t hat ae and awb are in lock state for optimum still image capture. cb lock state cb channel fsm status. ?00? means that awb cb plane is in lock state cr lock state cr channel fsm status. ?00? means that awb cr plane is in lock state y frame mean [yfmean : 7dh : ro] 7 6 5 4 3 2 1 0 y frame mean ro ro ro ro ro ro ro ro the register reports current y plane frame mean value. cb frame mean [cbfmean : 7eh : ro] 7 6 5 4 3 2 1 0 cb frame mean ro ro ro ro ro ro ro ro the register reports current cb plane frame mean value.
HV7131GP 2004/10/29 v2.4 42 cr frame mean [crfmean : 7fh : ro] 7 6 5 4 3 2 1 0 cr frame mean ro ro ro ro ro ro ro ro the register reports current cr plane frame mean value. minimum anti-banding gain [bndgmin : 80h : 08h] 7 6 5 4 3 2 1 0 minimum anti-banding gain 0 0 0 0 1 0 0 0 the register specifies the minimum limit to whic h ae may decrease preamp gain or y digital gain in order to get optimum exposure value while anti -banding mode is enabled and the following condition is met. ae lock boundary < (y frame mean - ae target) < ae unlock boundary. maximum anti-banding gain [bndgmax : 81h : 18h] 7 6 5 4 3 2 1 0 maximum anti-banding gain 0 0 0 1 1 0 0 0 the register specifies the maximum limit to whic h ae may increase preamp gain or y digital gain in order to get optimum exposure value while anti -banding mode is enabled and the following condition is met. ae lock boundary < (ae target - y frame mean) < ae unlock boundary. integration-scan offset high [isofsh : 82h : ro] 7 6 5 4 3 2 1 0 integration-scan offset high ro ro ro ro ro ro ro ro integration-scan offset middle [isofsm : 83h : ro] 7 6 5 4 3 2 1 0 integration-scan offset middle ro ro ro ro ro ro ro ro integration-scan offset low [isofsh : 84h : ro]
HV7131GP 2004/10/29 v2.4 43 7 6 5 4 3 2 1 0 integration-scan offset low ro ro ro ro ro ro ro ro the register represents time offset between int egration plane and scan plane. the value should be the same as the value specified by in tegration time register(63h ? 65h). awb luminance high boundary [awbluhi : 8ah : c8h] 7 6 5 4 3 2 1 0 awb luminance high boundary 1 1 0 0 1 0 0 0 during cb/cr frame mean value calculation, awb disca rds pixel of which luminance value is larger than this register value. awb luminance low boundary [awblulo : 8bh : 0ah] 7 6 5 4 3 2 1 0 awb luminance low boundary 0 0 0 0 1 0 1 0 during cb/cr frame mean value calculation, awb di scards pixel of which luminance value is smaller than this register value. awb valid number [awbno : 8ch : 02h] 7 6 5 4 3 2 1 0 awb valid number 0 0 0 0 0 0 1 0 awb update when the number of valid color pixe l is larger than (this valid value x 64). dark bad pixel concealment mode [dpcmode : 90h : 0h] 7 6 5 4 3 2 1 0 reserved dark bad pixel concealment mode 0 0 0 0 0 0 0 0 dark bad pixel concealment 10 dark bad pixel concealment is always performed.
HV7131GP 2004/10/29 v2.4 44 01 dark bad pixel concealment is performed when integration time (63h-65h) exceeds dark bad integration time(91h-93h) mode 11, 00 dark bad pixel concealment is turned off dark bad integration time high [dpcinth : 91h : 13h] 7 6 5 4 3 2 1 0 dark bad integration time high 0 0 0 1 0 0 1 1 dark bad integration time middle [dpcintm : 92h : 12h] 7 6 5 4 3 2 1 0 dark bad integration time middle 0 0 0 1 0 0 1 0 dark bad integration time low [dpcintl : 93h : d0h] 7 6 5 4 3 2 1 0 dark bad integration time low 1 1 0 1 0 0 0 0 dark bad integration time registers(91h-93h) spec ify minimum integration time value(63h-65h) where dark bad concealment operation is performed when dark bad pixel concealment mode is ?01 (binary)?. dark bad g threshold [dpcgth : 94h : 0ch] 7 6 5 4 3 2 1 0 dark bad g threshold 0 0 0 0 1 1 0 0 the register value specify the current g pixel?s di fferential value with neighboring g pixels, and is used to check whether current g pixel is dark bad pixel or not. dark bad c threshold [dpcgth : 95h : 0ch] 7 6 5 4 3 2 1 0 dark bad c threshold 0 0 0 0 1 1 0 0
HV7131GP 2004/10/29 v2.4 45 the register value specify the current r or b pixe l?s differential value with neighboring g pixels, and is used to check whether current r or b pixel is dark bad pixel or not. frame timing for clear description of frame timing, clocks? acronym and relation are reminded in here again. < clock acronym definition > mcf : master clock frequency dcf : divided clock frequency scf : sensor clock frequency icf : image processing clock frequency vcf : video clock frequency lcf : line clock frequency < clock frequency relation > mcf : mcf dcf : mcf/clock division scf : dcf/2 icf scf for 3x3 interpolation, scf/2 for 1/4 subsampling mode scf/4 for 1/16 subsampling mode vcf : icf for 16bit output, icf*2 for 8bit output lcf : 1/(hblank period + hsync period) hblank period : hblank time register value * (1/scf) hsync period : hsync active time < frame time calculation > core frame time is (idle slot + video height * lcp) and real frame time is resolved as follows. when integration time > core frame time, real fr ame time is (integration time + vblank * lcp), otherwise is (core frame time + vblank * lcp). 1. 3x3 color interpolation timing 3x3 color interpolation frame timing related parameters master clock frequency(mcf) 20mhz divided clock frequency(dcf) mcf/1 = 20mhz sensor clock frequency(scf) dcf/2 = 10mhz sensor clock period(scp) 1/10mhz = 100ns window width 640 window height 480 hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 848 scps output bus width 8bit vga video output frequency scf * 2 = 20mhz
HV7131GP 2004/10/29 v2.4 46 final video output size 640x480 . . if integration time < core frame time, real frame time is 2 * (208 + 640) scps + 480 * (208 + 640) scps + 8 * (208 + 640) scps = 415520 scps = 0.041552sec else real frame time is integration time * scps + 8 * (208 + 640) scps. hold slot in frame timing appears only if integr ation time is larger than core frame time. idle slot(2lcps + (512+hblank)*4) lcp(848 scps) hblank (208 scps) hsync (640 scps) active data: 640 ea vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video lines is active every lcp, that is, 480 video lines for 480 lcps
HV7131GP 2004/10/29 v2.4 47 y cb y cr y cb y cr one active video line is equal to one line clock period(lcp) = 848 scps hblank (208 scps) hsync (640 scps) scf (10mhz) vcf[vclk] (20mhz) y[7:0] 2. 1/4 subsampling timing 1/4 subsampling frame timing related parameters master clock frequency(mcf) 20mhz divided clock frequency(dcf) mcf/1 = 20mhz sensor clock frequency(scf) dcf/2 = 10mhz sensor clock period(scp) 1/10mhz = 100ns window width 640 window height 480 hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 848 * 2 scps output bus width 8bit sif video output frequency scf * 1 = 10mhz final video output size 320x240 in 1/4 subsampling mode, valid video data is produced every other line, i.e. for 480 lcps, active video lines are 240. hsync active time is equal to hsync active time of 3x3 color interpolation mode, but video clock frequency is half of 3x3 color interpolati on mode?s to produce half size output in horizontal direction.
HV7131GP 2004/10/29 v2.4 48 hblank (208 scps) hsync (640 scps) active data: 320 ea vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video lines is active every other lcp, that is, 240 video lines for 480 lcps idle slot (( 512+hblank)*4 ) 1 idle line (848scps) y cb y cr one active video line is equal to two line clock period(lcp) = (848 x 2) scps hblank (208 scps) hsync (640 scps) scf (10mhz) vcf[vclk] (10mhz) y[7:0] 1 idle line (848 scps) 3. 1/16 subsampling timing 1/16 subsampling frame timing related parameters master clock frequency(mcf) 20mhz divided clock frequency(dcf) mcf/1 = 20mhz sensor clock frequency(scf) dcf/2 = 10mhz sensor clock period(scp) 1/10mhz = 100ns
HV7131GP 2004/10/29 v2.4 49 window width 640 window height 480 hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 848 * 4 scps output bus width 8bit qsif video output frequency scf / 2 = 5mhz final video output size 160x120 in 1/16 subsampling mode, valid video data is produced every four line, i.e. for 480 lcps, active video lines are 120. hsync active time is equal to hsync active time of 3x3 color interpolation mode, but video clock frequency is a quarter of 3x3 color interpolation mode?s to produce a quarter size output in horizontal direction. hblank (208 scps) hsync (640 scps) active data: 160 ea vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video data is active at last 1 lcp period of every 4 lcps period, that is, 120 video lines for 480 lcps idle slot ( (512+hblank)*4 ) 3 idle lines (3 * 848 scps)
HV7131GP 2004/10/29 v2.4 50 y cb one active video line is equal to four line clock period(lcp) = 848 x 4 scps hblank (208 scps) hsync (640 scps) scf (10mhz) vcf[vclk] (5mhz) y[7:0] 3 idle lines (3 * 848 scps) anti-banding configuration for anti-banding mode to work correctly, the followi ng registers should be configured to the appropriate values. ae mode 60h anti-banding enable[7] ae anti-banding step 6a-6ch scf / (2 x power line frequency) ae integration time limit 6d-6fh the val ue should be multiples of ae anti-banding step when anti-banding is enabled, ae initializes integrat ion time registers[63-65h] to 4 x anti-banding step value[6a-6ch], and integration increment/decrem ent amount is set to anti-banding step value in order to remove anti-banding noise caused by intrin sic energy waveform of light sources. banding noise is inherent in cmos image sensor that adopts rolling shutter scheme for image acquisition.
HV7131GP 2004/10/29 v2.4 51 data output timing and interface y[7:0] vclk c[7:0] hsync x y0 y1 y2 x cb0 cr0 cb1 4ns ~ 5ns 14ns ~ 15ns mclk as specified in the above data output timing diagram, the timing margin between video clock pin (vclk) and data pins (y[7:0] or c[7:0]) is about 4ns ~ 5ns. this margin may be sufficient or not according to how much video clock and data pins are delayed internally in the backend chip, respectively. to safely latch the data output in the backend chip, it is recommended that data be latched at negative edge of vclk. the above timing marg in diagram represents 16bit output interface, but is also valid for 8bit output interface. output data format output format is controlled by configuring out put format register[31h]. configurable options are specified again for your reference. output format [outfmt : 31h : 39h] 7 6 5 4 3 2 1 0 reserved reserved cb first y fi rst 8 bit output reserved ycbcr 4:4:4 ycbcr 4:2:2 0 0 1 1 1 0 0 1 cb first cb pixel in front of cr pi xel in 16bit or 8bit video data output modes y first y pixel in front of cb and cr pixe ls in 8bit video output mode. this option is meaningful only with 8bit output mode. 8 bit output image data is produced only in y[7:0]. c[7:0] should be discarded
HV7131GP 2004/10/29 v2.4 52 ycbcr 4:4:4 ycbcr 24bit data for a pixel is produced with 16bit output mode. with color space conversion disabled, rgb 24bit dat a for a pixel is produced in this mode. this mode is meaningful only with 16bit output mode. ycbcr 4:2:2 ycbcr data for a pixel is produced with 8/16 output mode output timings for general configurations are descri bed below. slot named as ?x? means that it is has no meaningful value and should be discarded. 1. ycbcr 4:2:2 with 16bit output register bit configurations: 16bit output, cb first, ycbcr 4:2:2 y[7:0] vclk c[7:0] hsync x y0 y1 y2 y3 y4 y5 x cb0 cr0 cb1 cr1 cb2 cr2 2. ycbcr 4:2:2 with 8bit output register bit configurations: 8bit out put, y first, cb first, ycbcr 4:2:2 y[7:0] vclk c[7:0] hsync x x y0 cb0 y1 cr0 y2 cb1 y3 cr1 y4 cb2 y5 cr2 x x x x x x x x x x x x x x 3. 24bit ycbcr 4:4:4 output register bit configurations : 8bit output, y first, cb first, ycbcr 4:4:4, and color space conversion enabled
HV7131GP 2004/10/29 v2.4 53 y[7:0] vclk c[7:0] hsync x x y0 x y1 x y2 x y3 x y4 x y5 x x x cb0 cr0 cb1 cr1 cb2 cr2 cb3 cr3 cb4 cr4 cb5 cr5 4. 24bit rgb 4:4:4 output register bit configurations : 8bit output, y first, cb first, ycbcr 4:4:4, and color space conversion disabled y[7:0] vclk c[7:0] hsync x x g0 x g1 x g2 x g3 x g4 x g5 x x x b0 r0 b1 r1 b2 r2 b3 r3 b4 r4 b5 r5 bayer data format sctra[1:0] is set to bayer mode - when bayer output mode is selected, window width x window height raw image data are produced with the following sequence. after vsync goes low state, the first hsync line of a frame is activated with b pixel data appearing first when both of column start address and row start address are even. y[7:0] even line vclk y[7:0] odd line hsync x b g b g b g x g r g r g r
HV7131GP 2004/10/29 v2.4 54 i2c chip interface register write sequences one byte write s 22h a 01h a 03h a p *1 *2 *3 *4 *5 *6 *7 *8 set "sensor control a" register into window mode *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 01h [sub-address] *5. read: acknowledge from sensor *6. drive: 03h [video mode : cif *7. read: acknowledge from sensor *8. drive: i2c stop condition multiple byte write using auto address increment s 22h a 6ah a 51h a 61h a p *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 set "ae integration step high/low" regist er as 5161h with auto address increment *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 6ah [sub-address] *5. read: acknowledge from sensor *6. drive: 51h [ae integration step high] *7. read: acknowledge from sensor *8. drive: 61h [ae integration step low] *9. read: acknowledge from sensor *10. drive: i2c stop condition
HV7131GP 2004/10/29 v2.4 55 register read sequence s 22h a 50h a s 23h a data of 50h a p *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 read "reset level control" register from HV7131GP *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device addr ess + r/w bit(be careful. r/w=0)] *3. read: acknowledge from sensor *4. drive: 50h [sub-address] *5. read: acknowledge from sensor *6. drive: i 2 c start condition *7. drive: 23h(001_0001 + 1) [device addr ess + r/w bit(be careful. r/w=1)] *8. read: acknowledge from sensor *9. read: read ?reset level control value? from sensor *10. drive: acknowledge to sensor. if there is more data bytes to read, sda should be driven to low and data read states(*9, *10) is repeated. otherwi se sda should be driven to high to prepare for the read transaction end. *11. drive: i2c stop condition ac/dc characteristics absolute maximum ratings symbol parameter units min. max. vdpp digital supply voltage volts -0.3 7.0 vapp analog supply voltage volts -0.3 7.0 vipp input signal voltage volts -0.3 7.0 top operating temperature c -30 70 tst storage temperature c -40 85 caution: stresses exceeding the absolute maximum ratings may induce failure.
HV7131GP 2004/10/29 v2.4 56 dc characteristic symbol parameter units min. typical. max. conditions¬e v dd internal operation supply voltage volt 2.6 - 3.0 - i dd operating current consumption ma - 40 at 15fps (12.5mhz) hsi dd hard sleep static current consumption ua - 48 at 15fps (12.5mhz) ssi dd soft sleep static current consumption ua - - 276 at 15fps(12.5mhz) v ih input voltage logic "1" volt 2.0 - 3.0 - v il input voltage logic "0" volt 0 - 0.8 - v oh output voltage logic "1" volt 2 - - at ioh = -4ma v ol output voltage logic "0" volt - - 0.4 at iol = 4ma iih input high current ua -10 - 10 - iil input low current ua -10 - 10 - t a ambient operating temperature celsiu s -10 - 50 - cin input capacitance pf 5 - - - cout output capacitance pf - - 30 - cbid bi-directional buffer capacitance pf - - 30 - r epud external pull-up / pull-down resistance ohm - - 20k 1) note.1) r e pud is just applied to sda and sck pin. and if r e pud is less than 20k ohm, power consumption is increased. ac operating conditions symbol parameter max operation frequency units notes mclk main clock frequency 25 mhz 1,2 sck i 2 c clock frequency 400 khz 3 1. mclk may be divided by internal clock division logic for easy integration with high speed video codec system. 2. frame rate : 30 frames/sec at 25mhz, hblank = 208, vblank = 8 3. sck is driven by host processor. for the detail seri al bus timing, refer to i2c chip interface section
HV7131GP 2004/10/29 v2.4 57 output ac characteristics all output timing delays are measured with output load 60[pf]. output delay includes the internal clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. due to the variable valid time delay of the output, video output signals y[7:0], c[7:0], hsync, and vsync may be la tched in the negative edge of vclk for the stable data transfer between the image sensor and video codec. y/c[7:0] vclk x data 0 data 1 data 2 hsync data 3 4ns ~ 5ns
HV7131GP 2004/10/29 v2.4 58 i2c bus timing sda sck stop start t buf t low t r t hd; s ta t hd; d at t high t su; d at t su; s ta t su; s to stop start t f t hd; s ta parameter symbol min. max. unit sck clock frequency f sck 0 400 khz time that i 2 c bus must be free before a new transmission can start t buf 1.2 - us hold time for a start t hd ;s ta 1.0 - us low period of sck t low 1.2 - us high period of sck t high 1.0 - us setup time for start t su ;s ta 1.05 - us data hold time t hd ;d at 0.1 - us data setup time t su ;d at 250 - ns rise time of both sda and sck t r - 250 ns fall time of both sda and sck t f - 300 ns setup time for stop t su ;s to 1.05 - us capacitive load of sck/sda c b - 30 pf
HV7131GP 2004/10/29 v2.4 59 electro-optical characteristics - color temperature of light source: 3200k / ir cu t-off filter (cm-500s, 1 mm thickness) is used. soldering infrared(ir) / convection solder reflow condition parameter units min. typical max. note peak temperature range celsius - 230 240 1) note: 1) time within 5 celsius of actual peak temperature, 10sec parameter units min. typical max. note sensitivity mv / lux x sec 3000 green pixel dark signal mv 12 1/10? , 60 output saturation signal mv 1000
HV7131GP 2004/10/29 v2.4 60 clcc package specification
HV7131GP 2004/10/29 v2.4 61 * to the matter concerning package, wafer business companies are unrelated contents. magnachip semiconductor ltd. * contact point * cis marketing team 891 daechi-dong kangnam-gu seoul 135-738 korea tel: 82-2-3459-5577 fax: 82-2-3459-5580 e-mail : hanho1.lee@magnachip.com

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